Hello, kevin_intel
Thanks for shedding some light; I was carried away by this document Quick Reference Guide to 4th Generation Intel® Core™ Processor Graphics (formerly codenamed Haswell) | Intel® Developer Zone and the way it referred to "Deep Color" and x.v.Color, and until I tried to understand what you meant by "graphics controller", I finally determined that the Flexible Display Interface (FDI) is the actual bottleneck, as shown in paragraph 3 of section 2.7 of datasheet volume 1 for desktop & mobile (8 bits per color limit), whereas section 2.6 goes at length to describe how wonderful the interface is, supporting deep color to numerous displays up to 4K.
So the issue is between source & sink, as the sink is indeed marvelous, yet the current source implementation can give 32 bits per pixel (e.g. 8 bits red, 8 bits green, 8 bits blue and 8 bits transparency), yet unable to pipe & transcode 30 bits per pixel (10 bits red, 10 bits green and 10 bits blue).
Given how ubiquitous deep color screens are, as evidenced by HDMI 1.3 revision in 2006 (3 days after Blu-Ray was finalized at 8 bits per color !), and the very common use of DisplayPort (or ThunderBolt) on 4th Gen core motherboards, it did not occur to me that the FDI stage design would be this way. Looks like most manufacturers did not know either.
At least you saved me a lot of time playing with edid/cea861 modifications.
Do you know whether the Xeon P5100 implementation has the same FDI limitation ?
Regards,
Christopher